(a) Field of the Invention
The present invention relates to a thin film transistor array panel for a liquid crystal display, and a method of manufacturing the same.
(b) Description of the Related Art
Generally, a liquid crystal display (“LCD”) is one of the most widely used flat panel displays. The LCD has two glass substrates with electrodes formed thereon, and a liquid crystal layer interposed between the two substrates. Voltages are applied to the electrodes to re-orient liquid crystal molecules in the liquid crystal layer, thereby controlling the transmittance of light.
One of panels of an LCD has thin film transistors (“TFTs”) for switching the voltages applied to the electrodes, and is called the “TFT array panel.” In addition to the TFTs, the TFT array panel has signal lines including gate lines and data lines, and gate pads and data pads for transmitting signals to the gate and the data lines after receiving the signals from an external source. A plurality of pixel electrodes are formed at pixel areas defined by the intersections of the gate lines and the data lines such that they are electrically connected to the TFTs.
In order to enhance the charge storage capacity of pixels, a storage capacitor is provided at the LCD by way of a previous gate type or a separate wire type.
The previous gate type forms a storage capacitor by overlapping a pixel electrode with a neighboring gate line while interposing an insulating layer therebetween. By contrast, the separate wire type forms a storage capacitor by overlapping a pixel electrode with a separate storage electrode line while interposing an insulating layer therebetween. The separate wire type has an advantage that it reduces the signal delay of a 30-40 inch wide screen LCD.
Meanwhile, several photolithography steps are required for manufacturing a wide screen LCD. The substrate is partitioned into two or more areas, which are exposed to light in turn, and the degree of misalignment is different between the partitioned areas after the completion of the light exposure. Therefore, the brightness distribution is non-uniform between the partitioned areas and it is resulted from two reasons. The first reason is the distance difference between the data line and the pixel electrode in the respective partitioned areas due to the misalignment. For example, a pixel voltage of a pixel in a partitioned area with a pixel electrode closer to the right data line is different from that of a pixel in another partitioned area with a pixel electrode closer to the left data line. The second reason is the difference of parasitic capacitance generated between the gate electrode and the drain electrode in the respective partitioned areas due to the misalignment. The parasitic capacitance in a partitioned area with the closely spaced gate and drain electrodes is different from that in a partitioned area with the distantly spaced gate and drain electrodes, and the difference causes the kick-back voltage difference and thus the pixel voltage difference.